Shenggao Li, PhD - Director at TSMC

About

Dr. Shenggao Li is a Director with the Mixed-Signal and RF Solutions Division at TSMC, North America, where he focuses on energy-efficient interconnects, including chiplet and 3D-IC interconnects such as UCIe and HBM physical layers, high-speed ADCs for wireless and wireline communications, and most recently, 200-400G co-packaged optics.

With over 20 years of experience delivering innovative solutions to products, Dr. Li brings deep knowledge of analog and mixed-signal design theory and techniques, RF design, phase-locked loops, and high-speed electronics. He is recognized as an expert in the area of high-speed SerDes, chiplet, 3DIC, and optical interconnects.

Prior to TSMC, Dr. Li served as a Principal Engineer, Section Leader, and Director of IP/SoC Strategy at Intel, where he led PCIe Gen3.0/4.0/5.0, UPI, and CXL PHY implementation and high-volume manufacturing across 5 generations of Xeon CPU products (32nm to 7nm), and drove strategic consolidation of redundant IP efforts.

                    Education
                    Business Executive Program
Corporate Innovation
Stanford University GSB
PhD, Electrical Engineering
Ohio State University (Columbus)
MS
Tsinghua University (Beijing)
BS
Northwestern Polytechnical University (Xi'an)

                

Selected Publications

2026

A 32Gb/s 12.35Tb/s/mm² 0.36pJ/b UCIe-Like Die-to-Die Interface Featuring Edge-Triggered Transceivers in 3nm with Active LSI Packaging

IEEE International Solid-State Circuits Conference (ISSCC 2026)

Wei-Chih Chen, Mu-Shan Lin, Chien-Chun Tsai, Shenggao Li, et al.

2025

Design and Implementation of RF Circuit Under Inductor (CUI) in CMOS Technologies

IEEE Transactions on Microwave Theory and Techniques (Early Access)

Hsieh-Hung Hsieh, Shenggao Li, et al.
Design Technology Co-optimization for RF/mmWave Circuits with Circuit under Inductor (CUI) in FinFET CMOS Technologies

IEEE Radio Frequency Integrated Circuits Symposium (RFIC 2025)

Hsieh-Hung Hsieh, Shenggao Li, et al.
A 32Gb/s 10.5Tb/s/mm 0.6pJ/b UCIe-Compliant Low-Latency Interface in 3nm Featuring Matched-Delay for Dynamic Clock Gating

IEEE International Solid-State Circuits Conference (ISSCC 2025)

Mu-Shan Lin, Shenggao Li, et al.
UCIe-Compliant Chiplet Interconnect Design Leveraging Cutting-Edge Packaging Technologies

IEEE Custom Integrated Circuits Conference (CICC 2025)

Yu-Jie Huang, Mu-Shan Lin, Shenggao Li, et al.
Fast and Accurate Jitter Amplification Modeling With Variable Pulse Width Response

IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Vol. 15(4)

Shenggao Li, Maher Amer
TSMC in the Silicon Photonics Era - an Electrical Perspective

Optical Fiber Communication Conference (OFC 2025)

Mikael Sahrling, Shenggao Li, Frank Lee, Stefan Rusu

2024

High-Bandwidth Chiplet Interconnects for Advanced Packaging Technologies in AI/ML Applications: Challenges and Solutions

IEEE Open Journal of the Solid-State Circuits Society

Shenggao Li, Mu-Shan Lin, Wei-Chih Chen, Chien-Chun Tsai
Current Mirrors with Tapered Stacked-Gates for Area Saving or Noise Improvement in 3nm FinFET Process

IEEE Symposium on VLSI Technology and Circuits 2024

Chu-En Hsia, Shenggao Li, et al.
A 0.296pJ/bit 17.9Tb/s/mm² Die-to-Die Link in 5nm/6nm FinFET on a 9μm-Pitch 3D Package

IEEE Symposium on VLSI Technology and Circuits 2024

Mu-Shan Lin, Shenggao Li, et al.

2022

Interconnect in the Era of 3DIC

IEEE Custom Integrated Circuits Conference (CICC 2022)

Shenggao Li et al.

2018

A Power and Area Efficient 2.5-16 Gbps Gen4 PCIe PHY in 10nm FinFET CMOS

IEEE Asian Solid-State Circuits Conference (A-SSCC 2018)

Shenggao Li, Fulvio Spagna, Ji Chen, Xiaoqing Wang, et al.

2014-2015

A 22nm 15-Core Enterprise Xeon Processor Family

IEEE International Solid-State Circuits Conference (ISSCC 2014) & IEEE Journal of Solid-State Circuits, Vol. 50(1), 2015

Stefan Rusu, Harry Muljono, David Ayers, Simon M. Tam, Wei Chen, Aaron Martin, Shenggao Li, et al.

2011

Clock Generation for a 32nm Server Processor with Scalable Cores

IEEE International Solid-State Circuits Conference (ISSCC 2011)

Shenggao Li, Ashwin Krishnakumar, Edward Helder, Roan Nicholson, Vivian Jia

2003

A 10-GHz CMOS Quadrature LC-VCO for Multirate Optical Applications

IEEE Journal of Solid-State Circuits, Vol. 38(10), pp. 1626-1634

Shenggao Li, Issy Kipnis, Mohammed Ismail

Corporate Publications

TSMC DTP Conference

A 23fJ/bit PAM4 224Gbps Non-retimed Optical Receiver for COUPE Application

Gaurav Yadav, Mu-Shan Lin, Chien-Chun Tsai, Shenggao Li

DTP Conference 2025
A 12bit 400MS/s TDC-Assisted SAR ADC

Manoj Bharat Vasekar, Mei-Chen Chuang, Shenggao Li

DTP Conference 2025
Topology Transferable Graph Neural Networks with Reinforcement Learning for Circuit Scalable DTCO

Chih-Chiang Lin, Mu-Shan Lin, Chien-Chun Tsai, Shenggao Li

DTP Conference 2025
An A16 SPR 0.246pJ/bit 64Gb/s/pin UCIe-Compliant Receiver with PWM-based DFE and Efficient Per-lane DCC/QEC Calibration

Yu-Jie Huang, Mu-Shan Lin, Chien-Chun Tsai, Shenggao Li

DTP Conference 2025 (Best Paper)
A 64Gbps 21Tb/s/mm 0.548pJ/bit 3nm Chiplet System on Both CoWoS-L and CoWoS-R Advanced Packaging and AI-Driven Prediction for Next Generation Multi-Stacked 2.5D Packaging

Shu-Chun Yang, Wei-Chih Chen, Chien-Chun Tsai, Shenggao Li

DTP Conference 2025 (Best Presentation)
A 32Gb/s 10.5Tb/s/mm 0.34pJ/bit Chiplet IO Using CoWoS-L Active-LSI with Edge Trigger Transceiver in 3nm

Chin-Hua Wen, Mu-Shan Lin, Chien-Chun Tsai, Shenggao Li

DTP Conference 2024 (Best Paper)
A 2-16GHz 0.66° 85-fs p-p Jitter Precise Quadrature Clock Generator with Chopping Cancellation and Dynamic Gating Mode

Wei-Shuo Lin, Wei-Chin Chen, Chien-Chun Tsai, Shenggao Li

DTP Conference 2024
Ring-Amplifier-Based CDAC Reference Buffer with Auxiliary Stages for Fast Settling Improvements

Shang-Hsien Yang, Mei-Chen Chuang, Shenggao Li

DTP Conference 2024
A 64Gb/s 0.232pJ/b 3nm NRZ Transmitter Using CoWoS-L with Capacitive Equalization and Edge-Complementary Zero-Crossing Sampling

Sheng-Tsung Lai, Shu-Chun Yang, Han-Tzung Ke, Wei-Chih Chen, Chien-Chun Tsai, Shenggao Li

DTP Conference 2024
Wafer-Scale Optical Interconnects: All-to-all Link for Bandwidth of 10TBps per ASIC and 3360TBps on a Wafer

Gaurav Vijay Yadav, Mu-Shan Lin, Chien-Chun Tsai, Shenggao Li

DTP Conference 2024
A 3nm 0.27pJ/bit 32Gb/s/pin UCIe-Compliant Receiver with Matched-delay Architecture and Deskew/Runtime Calibration

Yu-Jie Huang, Mu-Shan Lin, Chien-Chun Tsai, Shenggao Li

DTP Conference 2023 (Best Paper)
A 0.4pJ/b 32Gb/s Die-to-Die Link Using NRZ Transmitter with Arbitrary Clock Phases and Low Latency for 10.5Tb/s/mm UCIe Applications in 3nm FinFET

Chin-Hua Wen, Mu-Shan Lin, Chien-Chun Tsai, Shenggao Li

DTP Conference 2023
Statistical Bit Error Rate Analysis for Die to Die Interconnect – A Tutorial

Shenggao Li

DTP Conference 2023
Jitter Modeling and Analysis for High-Speed Communication Systems (A Tutorial)

Shenggao Li, Maher Amer

DTP Conference 2022
A 2.4mW 6b 400μm² 1.75GS/s SAR ADC with Delay-Reduction Schemes and Consolidated P/N Guard-Ring Pickup Tap in 5nm FinFET CMOS

Mei-Chen Chuang, Shenggao Li, et al.

DTP Conference 2022 (Best Presentation)
A 7nm 8Gb/s/pin LIPINCON Chiplet Interface with 2Tbit/s/mm Beachfront Bandwidth Density and 0.36pJ/bit Energy Efficiency for GPGPU Application

Yu-Jie Huang, Shenggao Li, et al.

DTP Conference 2022 (Best Paper)
A 5nm/6nm 16Gb/s/pin PAM4 Cross-Chiplets Link Achieving 1280GB/s Bandwidth, 0.296pJ/bit Energy Efficiency, and 17.9Tb/s/mm² Area Efficiency for 3DIC Applications

Mu-Shan Lin, Shenggao Li, et al.

DTP Conference 2021 (Best Paper)
Multi-Path 16GHz 8-phase Ring Oscillator with Better Voltage Sensitivity by 4nm Technology

Shenggao Li, et al.

DTP Conference 2021

Intel DTTC Conference

An All-Digital CMOS Ring-oscillator based Clock Data Recovery System for Multi-rate Serial Links

Shenggao Li, et al.

Intel DTTC 2017
Nonlinearity in a Non-integrating DFE Summer

Xiaoqing Wang, Shenggao Li

Intel DTTC 2017
The Pursuit of a Crosstalk Tolerant Forwarded-Clock System – A Case Study

Kai Xiao, Shenggao Li, et al.

Intel DTTC 2013
IVT PCIE/QPI DFE Summer – Post-Silicon Learnings and Design Optimization

Salman Latif, Shenggao Li, et al.

Intel DTTC 2013
LC-PLL with Digital Frequency Calibration and Improved HVM Screening

Roan Nicholson, Shenggao Li, et al.

Intel DTTC 2013
High-speed Low-power Clock Dividers for Phase-locked Loops (Tutorial)

Shenggao Li

Intel DTTC 2011

Patents

Granted Patents (2000-2024)

US10,848,353 - Multi-Tap Decision Feedback Equalizer (DFE) Architecture with Split-Path Summer Circuits

Granted: June 2019
US10,708,093 - Supply Voltage Adaptation Via Decision Feedback Equalizer

Granted: August 2018
US10,523,411 - Programmable Clock Data Recovery (CDR) System Including Multiple Phase Error Control Paths

Granted: March 2018
US10,181,969 - High Performance Receiver with Single Calibration

Granted: January 2019
US10,128,855 - Apparatus and Method for Clock Synchronization for Inter-Die Synchronized Data Transfer

Granted: November 2018
US10,075,308 - Supply Voltage Adaptation Via Decision Feedback Equalizer

Granted: September 2018
US10,063,253 - Summer Circuit Including Linearized Load

Granted: August 2018
US9,973,176 - Circuits for Digital and Analog Controlled Oscillators

Granted: May 2018
US9,735,813 - Method and Apparatus for Signal Edge Boosting

Granted: August 2017
US9,641,184 - Compensation for Digitally Controlled Oscillator Apparatus and Method

Granted: May 2017
US9,531,393 - Phase Frequency Detector

Granted: December 2016
US9,455,727 - Open-Loop Voltage Regulation and Drift Compensation for Digitally Controlled Oscillator (DCO)

Granted: September 2016
US9,413,364 - Apparatus and Method for Clock Synchronization for Inter-Die Synchronized Data Transfer

Granted: August 2016
US9,379,743 - Method and Apparatus for Signal Edge Boosting

Granted: June 2016
US9,215,104 - Floating Taps for Decision Feedback Equalizer

Granted: December 2015
US9,071,253 - Compensation for Digitally Controlled Oscillator App. and Method

Granted: June 2015
US8,981,822 - High Speed Dual Modulus Divider

Granted: March 2015
US8,957,705 - Phase Frequency Detector

Granted: February 2015
US8,843,093 - Low Power Squelch Detector Circuit

Granted: September 2014
US8,749,289 - Multi-Phase Clock Generation Apparatus and Method

Granted: June 2014
US8,520,428 - Combined Data Level-Shifter and De-Skewer

Granted: August 2013
US7,421,052 - Oscillator Frequency Selection

Granted: September 2008
US7,366,427 - Line Driver with Variable Bandwidth Control

Granted: April 2008
US6,954,110 - Replica Cell for Ring Oscillator

Granted: October 2005
US6,870,432 - Unilateral Coupling for a Quadrature Voltage Controlled Oscillator

Granted: March 2005
US6,853,254 - Anti-Deadlock Circuit and Method for Phase-Locked Loops

Granted: February 2005

Recent Patent Applications (2020-2024)

Differential Magnetic Core Inductors in Silicon Wafer or THV/TGV

Joint provisional invention with Princeton University and U-Penn

Filed: July 2025
18/919,584 - 3D Die to Die Interconnect Clock Scheme

Filed: October 2024
18/912,708 - Universal Bump Map Assignment for 3D Lego Stacking

Filed: October 2024
18/815,990 - Synchronized Clock Distribution Between Two Vertically Stacked Dies

Filed: August 2024
18/779,308 - Settling-Time Reduction Technique for Continuous Time Comparators

Filed: July 2024
18/772,677 - Clock Scheme for Die to Die Interconnect with Maximal I/F Timing Robustness

Filed: July 2024
18/768,508 - 3D Die Stacking and Bump Organization Method

Filed: July 2024
18/749,857 - Fine Granularity Control of Digitally Controlled Multi-Phase Delay Line and/or Ring Oscillator

Filed: June 2024
18/647,151 - In-situ Defect Detection and Monitoring with Ability to Boost ADC Accuracy

Filed: April 2024
18/623,579 - Chiplet Interconnect Method for Better EM/IR Performance

Filed: April 2024
18/436,643 - Using Honeycomb Structure for Die to Die Interconnect Structures

Filed: February 2024 (Issued)
18/517,078 - Defect Characterization and Monitoring Mechanism for Better Yield Analysis

Filed: November 2023
18/348,422 - A CDAC Control Method with Monotonicity Behavior

Filed: July 2023
18/300,862 - Using Honeycomb Structure for Die to Die Interconnect Structures

Filed: April 2023 (Issued)
18/239,839 - A Delay Line Implementation Method to Decouple High-Speed Path and Low Speed Control

Filed: August 2023
18/194,709 - 2.5D/3D Die to Die Integration Method to Enable Symmetry and High Bandwidth Density

Filed: April 2023
18/128,601 - Hybrid or Clusters of Power Bumps for Advanced Packaging

Filed: March 2023
17/825,360 - Eliminate Impact of TSV IR Drop for On-Die Voltage Regulator in 3DIC Integration

Filed: May 2022
17/688,966 - High-Voltage Design Methodology

Filed: March 2022

Invited Talks & Keynotes

Scaling AI Beyond Moore's Law: Serdes, 3D-IC Interconnects, Silicon Photonics, and DTCO for the Next Generation of Computing

Texas Semiconductor Summit, Texas A&M University

Keynote Speaker | March 26, 2026
Energy-Efficient Computing and Communication

Semiconductor Seminar Series, Wayne State University

Invited Speaker | March 25, 2026
Enabling Energy-Efficient High-speed Interconnects and Photonic Networks

Workshop: "Photonic Switching for AI Infrastructure: Architecting the Next-generation AI Fabric" | OFC 2026, Los Angeles Convention Center

Invited Panelist | March 18, 2026
Energy Efficient Computing and Communication: Perspectives on Chiplet Interconnects and Photonic Networks

MIT MTL CICS Seminar

Invited Speaker | February 18, 2026
Towards 400G+ bps Energy Efficient Optical Networks

MIT Rodgers RLE Forum Talks and Q&A

Invited Speaker | February 2026 | Link (MIT Zoom account required)
Towards 400G+ bps Per Lane Optical Networks for AI/ML Applications

SRC Jump 2.0 CUbiC (Center for Ubiquitous Connectivity), Columbia University

Invited Speaker | July 2025
Automotive Chiplets

College of Engineering Industry-University Partnership Forum, Wayne State University

Keynote Speaker | October 2024
Advanced Packaging and 3D-IC Interconnects

ISSCC 2023 Forum 1: Transceivers for Exascale

Invited Speaker | February 2023
Interconnect in the Era of 3DIC

IEEE Custom Integrated Circuits Conference (CICC 2022)

Industry Talk | April 2022

Awards & Recognition

📜

IEEE Senior Member

IEEE Solid-State Circuits Society

💡

50+ Patents

Clock, High-speed IO, Chiplet, and Heterogeneous Integration

TSMC Awards

2025 - TSMC Collaboration Award for COUPE EIC and SerDes Enablement
TSMC DTP Conference (2021-2025) - 4 Best Paper Awards, 2 Best Presentation Awards

Intel Product & Innovation Awards

Q2'19 - RX Latency Reduction for UPI in HSPHY
Q2'18 - Rapid Development of Novel Solution for MG's CDR State Restoration during PCIe4 Power-State Transitions
Q1'18 - DAC Mismatch Reduction for Dual-Patterning Metal Process in Intel 10nm
Q2'17 - PCIe 16Gbps, TBT 20.6Gbps, USB 10.3Gbps, DP 8Gbps Combo-PHY with Power-on Exit Beating Schedule
Q2'13 - Deploy PCIe & QPI Compliance Tests for Server Microprocessor Silicon PRQ
Q3'12 - Rapid Impact Analysis for Server Processors Following Client PLL Lock Failure Recall
Q3'12 - HSIO and PLL Yield Improvement for P1270 Server Products
Q2'11 - Robust CMOS I/Q Clock Generation and Wide Product Adoptions
Q3'11 - Flawless Execution and High Quality on Clock Design Enabling Successful SandyBridge-EP PRQ
Q3'08 - New Architecture for Reducing Ring-Stop to Ring-Stop Crossing Latency
Q2'05 - Implementation of an Electrical and Laser Link with Low Cost
Q1'05 - P1213 Gigabit-E PHY Post Silicon Yield Improvement
Q3'03 - 1st Generation of 10Gbps CMOS SONET Transceiver

Endorsements

What colleagues and collaborators say about working with Dr. Li.

"I have known Dr. Shenggao Li for over a decade, beginning with our collaboration at Intel, where he consistently demonstrated deep circuit insight and ability to drive innovative solutions. His work on PCIe SerDes introduced creative techniques that influenced several generations of PCIe standards, and his leadership of Intel's PHY teams helped shape multiple product lines. His teams' silicon results and feedback directly strengthened the PCIe ecosystem and improved the standard. After Dr. Li joined TSMC, our paths crossed again in the UCIe Consortium, where he now co‑chairs the Form Factor and Compliance Workgroup. He has been an energetic advocate for chiplet technologies and has led key technical pathfinding efforts, especially in form factor optimization, and bandwidth scaling. His expertise spans 2.5D/3D integration, optical I/O, and high‑speed mixed‑signal design. One of his recent papers in the Open Journal of the Solid‑State Circuits Society became the journal's most widely read publication. Beyond his technical depth, Dr. Li is an effective team builder with broad intellectual curiosity. He is an exceptional engineer, a collaborative leader, and a valuable contributor to our industry."

Zuoguo (Joe) Wu

Sr. Principal Engineer & I/O Circuit Architecture Manager, Intel Corporation

Sr. Principal Engineer & I/O Circuit Architecture Manager at Intel. Principal author of the UCIe specification and contributor to PCIe since Gen 3.0. Co-chairs the UCIe Electrical Workgroup. Holds 173 patents and 50+ publications. Ph.D., Electrical Engineering, Texas A&M University.

"I've had the pleasure of working closely with Shenggao on the Universal Chiplet Interconnect Express (UCIe) standard, where we collaborated on the physical bump map definition for advanced packaging modules. This was complex, high-stakes work that helped enable extremely high bandwidth-density targets (20+ Tb/s/mm), and Shenggao was instrumental in delivering a robust solution. Shenggao can dive deep into the physics and implementation tradeoffs of an interface without losing sight of system-level goals. He pushed for choices that met the spec and would scale cleanly for future generations, with the rigor needed to build a foundation the industry can rely on. In a cross-company standardization environment, he aligned diverse stakeholders, kept discussions grounded in first principles, and drove decisions without compromising technical quality. I also value his research on chiplet-system I/O. His publications are consistently clear and data-driven, turning complex architecture, signaling, and packaging co-optimization into practical, manufacturable guidance. His rare combination of technical depth, foresight, and collaborative leadership has left a lasting mark on the chiplet industry — and the work we built together is a testament to that."

Zhiguo Qian

Sr. Principal Engineer, Intel Corporation

Sr. Principal Engineer at Intel with 16+ years in advanced semiconductor packaging and high-speed I/O. Founding co-author of the UCIe standard and contributor to the IEEE EPS Heterogeneous Integration Roadmap. IEEE Senior Member. Ph.D., UIUC. 70+ papers, 60+ U.S. patents, 3,000+ citations.

"I am pleased to offer my strongest endorsement of Dr. Shenggao Li, an industry expert in mixed‑signal, RF, and high‑speed interconnect technologies. I worked closely with Shenggao across multiple generations of Intel Xeon server products, from 32nm to 7nm, and consistently witnessed his exceptional technical depth, strategic vision, and commitment to engineering excellence. At Intel, Shenggao played a pivotal role in developing and manufacturing PCIe Gen3/4/5, UPI, and CXL PHYs, guiding these interconnects from architecture through silicon bring‑up and production. His ability to turn complex analog and mixed‑signal concepts into robust, manufacturable IP was essential to the success of multiple Xeon products. He also demonstrated outstanding leadership as a Principal Engineer, Section Leader, and Director of IP/SoC Strategy. Shenggao is one of the most capable and forward‑thinking engineers I have worked with. His technical leadership and collaborative spirit make him an invaluable asset to any organization at the forefront of semiconductor innovation."

Yongping Fan

Retired Sr. Principal Engineer & Sr. Director of Foundry Circuit Technology, Intel Corporation

Retired Sr. Principal Engineer & Sr. Director of Foundry Circuit Technology at Intel, with 26+ years specializing in analog and mixed-signal circuits across 180nm to 18A nodes. Ph.D., Purdue University. 47 papers, 24 U.S. patents. Recipient of the ISSCC 2021 Lewis Winner Award for Outstanding Paper.

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About

Education

Experience

Director, Mixed-Signal and RF Solutions Division

Director, IP/SoC Strategy | Principal Engineer & Section Leader

Selected Publications

A 32Gb/s 12.35Tb/s/mm² 0.36pJ/b UCIe-Like Die-to-Die Interface Featuring Edge-Triggered Transceivers in 3nm with Active LSI Packaging

Design and Implementation of RF Circuit Under Inductor (CUI) in CMOS Technologies

Design Technology Co-optimization for RF/mmWave Circuits with Circuit under Inductor (CUI) in FinFET CMOS Technologies

A 32Gb/s 10.5Tb/s/mm 0.6pJ/b UCIe-Compliant Low-Latency Interface in 3nm Featuring Matched-Delay for Dynamic Clock Gating

UCIe-Compliant Chiplet Interconnect Design Leveraging Cutting-Edge Packaging Technologies

Fast and Accurate Jitter Amplification Modeling With Variable Pulse Width Response

TSMC in the Silicon Photonics Era - an Electrical Perspective

High-Bandwidth Chiplet Interconnects for Advanced Packaging Technologies in AI/ML Applications: Challenges and Solutions

Current Mirrors with Tapered Stacked-Gates for Area Saving or Noise Improvement in 3nm FinFET Process

A 0.296pJ/bit 17.9Tb/s/mm² Die-to-Die Link in 5nm/6nm FinFET on a 9μm-Pitch 3D Package

Interconnect in the Era of 3DIC

A Power and Area Efficient 2.5-16 Gbps Gen4 PCIe PHY in 10nm FinFET CMOS

A 22nm 15-Core Enterprise Xeon Processor Family

Clock Generation for a 32nm Server Processor with Scalable Cores

A 10-GHz CMOS Quadrature LC-VCO for Multirate Optical Applications

Corporate Publications

TSMC DTP Conference

A 23fJ/bit PAM4 224Gbps Non-retimed Optical Receiver for COUPE Application

A 12bit 400MS/s TDC-Assisted SAR ADC

Topology Transferable Graph Neural Networks with Reinforcement Learning for Circuit Scalable DTCO

An A16 SPR 0.246pJ/bit 64Gb/s/pin UCIe-Compliant Receiver with PWM-based DFE and Efficient Per-lane DCC/QEC Calibration

A 64Gbps 21Tb/s/mm 0.548pJ/bit 3nm Chiplet System on Both CoWoS-L and CoWoS-R Advanced Packaging and AI-Driven Prediction for Next Generation Multi-Stacked 2.5D Packaging

A 32Gb/s 10.5Tb/s/mm 0.34pJ/bit Chiplet IO Using CoWoS-L Active-LSI with Edge Trigger Transceiver in 3nm

A 2-16GHz 0.66° 85-fs p-p Jitter Precise Quadrature Clock Generator with Chopping Cancellation and Dynamic Gating Mode

Ring-Amplifier-Based CDAC Reference Buffer with Auxiliary Stages for Fast Settling Improvements

A 64Gb/s 0.232pJ/b 3nm NRZ Transmitter Using CoWoS-L with Capacitive Equalization and Edge-Complementary Zero-Crossing Sampling

Wafer-Scale Optical Interconnects: All-to-all Link for Bandwidth of 10TBps per ASIC and 3360TBps on a Wafer

A 3nm 0.27pJ/bit 32Gb/s/pin UCIe-Compliant Receiver with Matched-delay Architecture and Deskew/Runtime Calibration

A 0.4pJ/b 32Gb/s Die-to-Die Link Using NRZ Transmitter with Arbitrary Clock Phases and Low Latency for 10.5Tb/s/mm UCIe Applications in 3nm FinFET

Statistical Bit Error Rate Analysis for Die to Die Interconnect – A Tutorial

Jitter Modeling and Analysis for High-Speed Communication Systems (A Tutorial)

A 2.4mW 6b 400μm² 1.75GS/s SAR ADC with Delay-Reduction Schemes and Consolidated P/N Guard-Ring Pickup Tap in 5nm FinFET CMOS

A 7nm 8Gb/s/pin LIPINCON Chiplet Interface with 2Tbit/s/mm Beachfront Bandwidth Density and 0.36pJ/bit Energy Efficiency for GPGPU Application

A 5nm/6nm 16Gb/s/pin PAM4 Cross-Chiplets Link Achieving 1280GB/s Bandwidth, 0.296pJ/bit Energy Efficiency, and 17.9Tb/s/mm² Area Efficiency for 3DIC Applications

Multi-Path 16GHz 8-phase Ring Oscillator with Better Voltage Sensitivity by 4nm Technology

Intel DTTC Conference

An All-Digital CMOS Ring-oscillator based Clock Data Recovery System for Multi-rate Serial Links

Nonlinearity in a Non-integrating DFE Summer

The Pursuit of a Crosstalk Tolerant Forwarded-Clock System – A Case Study

IVT PCIE/QPI DFE Summer – Post-Silicon Learnings and Design Optimization

LC-PLL with Digital Frequency Calibration and Improved HVM Screening

High-speed Low-power Clock Dividers for Phase-locked Loops (Tutorial)

Patents

Granted Patents (2000-2024)

US10,848,353 - Multi-Tap Decision Feedback Equalizer (DFE) Architecture with Split-Path Summer Circuits

US10,708,093 - Supply Voltage Adaptation Via Decision Feedback Equalizer

US10,523,411 - Programmable Clock Data Recovery (CDR) System Including Multiple Phase Error Control Paths

US10,181,969 - High Performance Receiver with Single Calibration

US10,128,855 - Apparatus and Method for Clock Synchronization for Inter-Die Synchronized Data Transfer

US10,075,308 - Supply Voltage Adaptation Via Decision Feedback Equalizer

US10,063,253 - Summer Circuit Including Linearized Load

US9,973,176 - Circuits for Digital and Analog Controlled Oscillators

US9,735,813 - Method and Apparatus for Signal Edge Boosting

US9,641,184 - Compensation for Digitally Controlled Oscillator Apparatus and Method

US9,531,393 - Phase Frequency Detector

US9,455,727 - Open-Loop Voltage Regulation and Drift Compensation for Digitally Controlled Oscillator (DCO)

US9,413,364 - Apparatus and Method for Clock Synchronization for Inter-Die Synchronized Data Transfer

US9,379,743 - Method and Apparatus for Signal Edge Boosting

US9,215,104 - Floating Taps for Decision Feedback Equalizer

US9,071,253 - Compensation for Digitally Controlled Oscillator App. and Method

US8,981,822 - High Speed Dual Modulus Divider

US8,957,705 - Phase Frequency Detector

US8,843,093 - Low Power Squelch Detector Circuit

US8,749,289 - Multi-Phase Clock Generation Apparatus and Method

US8,520,428 - Combined Data Level-Shifter and De-Skewer

US7,421,052 - Oscillator Frequency Selection

US7,366,427 - Line Driver with Variable Bandwidth Control

US6,954,110 - Replica Cell for Ring Oscillator

US6,870,432 - Unilateral Coupling for a Quadrature Voltage Controlled Oscillator

US6,853,254 - Anti-Deadlock Circuit and Method for Phase-Locked Loops

Recent Patent Applications (2020-2024)

Differential Magnetic Core Inductors in Silicon Wafer or THV/TGV

18/919,584 - 3D Die to Die Interconnect Clock Scheme

18/912,708 - Universal Bump Map Assignment for 3D Lego Stacking